CovR: Coverage-Aware Hardware Verification via Reasoning-Guided Reinforcement Learning
Abdelatty, Nouh and Reda (Brown University) build CovR, an agentic testbench-generation system for RTL hardware verification that optimizes for coverage rather than functional correctness alone, and distill the resulting behavior into a student model with simulation-derived rewards.
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Coverage is the target, not a side effect. Prior LLM testbench work scores whether the generated bench compiles and passes. CovR rewards the fraction of design points the bench actually exercises, which is what verification engineers are paid to maximize.
The agentic loop supplies the training data. A self-reflection loop with simulator feedback and a strong teacher produces 16,514 specification-RTL-reasoning-testbench tuples, and that dataset is what makes coverage-aware supervised training possible at all.
RL on tool-derived rewards, then redeployment. The finetuned student reaches 93.81% cov@10 on VerilogEval and RTLLM V2.0 and 87.76% on CVDP, beating prior work by 7.97 and 3.59 points. Putting the student back inside the agentic refinement loop adds another pass, reaching 94.27% and 91.39%.
The coverage gain finds real bugs. Used as a plug-in stimulus engine, CovR raises coverage by 18.95% and mutation detection by 1.19%, and exposes 4.46% of failures that the correctness-optimized baseline missed.
Transfers to other verifier-gated domains. The recipe, an agentic loop generating data against a simulator, then RL on the simulator's own metric, applies anywhere a cheap executable checker scores more than pass/fail.
Abstract
Design verification remains one of the most resource-intensive stages of hardware development, often consuming up to 70% of the total design effort. While recent work has explored using Large Language Models (LLMs) to automate testbench generation, most existing approaches focus narrowly on functional correctness, overlooking the critical aspect of coverage quality. To bridge this gap, we present CovR, an agentic framework for automated testbench generation that combines self-reflection loops with simulation-based feedback to maximize coverage. Using this pipeline, we construct a large-scale dataset of 16,514 natural specification RTL reasoning testbench tuples with a strong teacher model, enabling coverage-aware supervision. Building on this, we propose a reinforcement learning (RL) framework tailored for coverage-driven testbench generation, leveraging tool-derived rewards from simulation and coverage feedback to optimize a student model. Experimental results show that the CovR finetuned model achieves 93.81% cov@10 on VerilogEval and RTLLM V2.0, and 87.76% cov@10 on CVDP, outperforming state-of-the-art approaches by 7.97% and 3.59%, respectively. Furthermore, deploying the finetuned model back into the agentic refinement pipeline further improves cov@10 to 94.27% on VerilogEval and RTLLM V2.0 and 91.39% on CVDP. Moreover, when integrated as a plug-in stimulus engine for full verification workflows, CovR improves coverage by 18.95% and mutation detection score by 1.19%, while revealing 4.46% undetected failures, highlighting the importance of optimizing for coverage in LLM-based hardware verification.