ChipMEM: Verification-Grounded Memory for EDA Agents
Abdulrahman AlRabah and colleagues at the University of Illinois Urbana-Champaign, with a co-author from NVIDIA, build ChipMEM, a memory layer for chip-design agents that stores a skill only after an EDA tool has verified it.
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Motivation. Prior skill-distillation and EDA-reward methods are usually scored on the same tasks that produced the experience, which rewards task-specific revision rather than knowledge that transfers.
Procedural memory. A skill enters the library only after it passes synthesis, simulation or formal checks, never on the model's own assessment.
Statistical memory. Hierarchical Beta estimates over tool-call outcomes rank recovery strategies that worked under comparable errors, and pass them to a recovery planner as advice.
Results with GPT-5.5. On RTLRewriter-Bench, 39/54 designs pass equivalence versus 35/54 without memory; on the 49-design short suite, mean area improvement is 8.69% versus 5.66%. On 20 held-out CVDP testbench tasks, a frozen procedural library reaches 20/20 accepted outcomes versus 18/20 without memory (single run per setting).
Shared adapter. The same memory interface serves RTL optimization and testbench generation while each domain keeps its own tools and acceptance criteria.
Abstract
Large language model (LLM)-based agents use Electronic Design Automation (EDA) tools to generate and revise register-transfer-level (RTL) designs under synthesis and verification feedback. Recent methods learn from this feedback by distilling reusable skills from execution traces or by training on rewards derived from EDA-tools. Both methods are typically evaluated on the tasks that produced the experience. Repeated access to benchmark feedback on the same task can reward task-specific revision rather than creating reusable knowledge that transfers. We introduce ChipMEM, a verification-grounded memory layer for EDA agents. It combines cross-task procedural memory with within-trajectory statistical guidance. Its procedural component distills and stores a skill only after it passes synthesis, simulation, or formal checks, rather than relying on model self-assessments. A Bayesian component maintains hierarchical Beta estimates over tool-call outcomes and ranks recovery strategies that succeeded under comparable errors. A common adapter applies the same memory interface to RTL optimization and testbench-generation agents while preserving each domain's tools and acceptance criteria. We measure performance on training tasks and evaluate whether learned skills transfer to unseen tasks. On RTLRewriter-Bench, under matched model and tool settings, ChipMEM produces equivalence-passing outputs on 39/54 scored designs versus 35/54 without memory; on the 49-design short suite, mean area improvement is 8.69% versus 5.66%. On held-out CVDP tasks, ChipMEM with a frozen procedural library achieves 20/20 accepted outcomes versus 18/20 without memory in a single evaluation per setting.